An active-matrix display device (e.g., active-matrix liquid crystal display) commonly display images by selecting pixels arranged in a matrix by the unit of pixel rows and writing a voltage corresponding to the display data into the selected pixels. For the selection of pixels in the unit of pixel rows, a gate bus line-driving circuit (hereafter, also referred to as a gate driver) is provided with a shift register that sequentially shifts an output signal (scanning signal) based on a clock signal.
The process of forming a thin film transistor (TFT) in a pixel may be utilized for forming a gate driver concurrently with the TFT in the pixel. For example, in a case where a TFT in a pixel is formed of amorphous silicon, preferably, a shift register included in a gate driver is also formed of the amorphous silicon for cost reduction. The gate driver may be monolithically formed on an array substrate these days.
Recently, the technique of one drop filling (ODF) has been developed as a method of filling a liquid crystal panel of a liquid crystal display with a liquid crystal material. In the ODF, a step of bonding two substrates and a step of injecting a liquid crystal material between the two substrates can be performed at the same time.
Exemplary techniques related to monolithic formation of a gate driver are mentioned below.
A disclosed device is a display device in which a display panel includes a first substrate provided with a plurality of gate lines and a plurality of data lines, a second substrate facing the first substrate, and a sealing material bonding the first substrate and the second substrate; and a gate driver includes a wiring portion for receiving a plurality of signals from the outside and a circuit portion outputting a driving signal in response to the plurality of signals, the wiring portion being provided with an opening for transmitting light incident through the back face of the first substrate for curing the sealing material (see Patent Literature 1). Patent Literature 1 teaches that the sealing material enhances the bonding power between the first substrate and the second substrate.
A disclosed unit is a driving unit including a circuit portion and a wiring portion, wherein the circuit portion has a plurality of stages cascade-connected to each other and outputs a driving signal in response to a plurality of control signals; the wiring portion has first and second signal wirings for receiving a plurality of control signals from the outside, a first connection wiring connecting the first signal wiring to the plurality of stages, and a second connection wiring connecting the second signal wiring to the plurality of stages; and the first signal wiring and the first and second connection wirings are provided in layers different from a layer of the second signal wiring (see Patent Literature 2).
A disclosed substrate is a display substrate including a gate wiring, a driving circuit portion, a signal wiring portion, a coupling wiring portion, and a contact portion, wherein the gate wiring is formed in a display region and crosses a source wiring; the driving circuit portion is formed in a peripheral region surrounding the display region and outputs a gate signal to the gate wiring; the signal wiring portion is formed adjacent to the driving circuit portion and extending in a running direction of the source wiring, and transmits a driving signal; the coupling wiring portion includes a first end portion overlapping with the signal wiring portion and a second end portion electrically coupled with the driving circuit portion; and the contact portion is formed on the signal wiring portion and electrically connects the first end portion of the coupling wiring portion to the signal wiring portion (see Patent Literature 3).
A disclosed circuit is a driving circuit including a plurality of driving stages and a dummy stage, wherein the plurality of driving stages are cascade-connected to each other by coupling an output terminal of each stage to a control terminal of the previous stage and sequentially outputs a switching element-driving signal to a plurality of driving-signal lines coupled with switching elements formed on pixels arranged in a matrix; and the dummy stage has a dummy output terminal coupled with a control terminal of the final stage, among the plurality of driving stages, and with a dummy control terminal thereof (see Patent Literature 4).
A disclosed device is a liquid crystal display device wherein a conventional first auxiliary capacitor trunk wiring is formed to have a narrower width, and a second auxiliary capacitor trunk wiring is newly provided and arranged at a position closest to the periphery of the substrate (see Patent Literature 5). According to the structure disclosed in the fifth embodiment and FIG. 13 of Patent Literature 5, a second auxiliary capacitor trunk wiring 440 and a DC voltage VSS wiring 420a, which has a largest width among the driving signal supply trunk wirings 420, have a slit-like opening.
A disclosed TFT is a TFT including a first capacitor formed by first and second capacitor electrodes, a second capacitor formed by third and fourth capacitor electrodes, a first lead wire, a second lead wire connected to a gate electrode, a third lead wire, a fourth lead wire, a first wiring, and a second wiring (see Patent Literature 6).
A disclosed shift register is a shift register configured by cascade-connected unit circuits, wherein each of the unit circuits includes an output transistor that is provided between a clock terminal and an output terminal and switches a mode whether or not a clock signal is transmitted in accordance with a gate potential and at least one control register that has one conductive terminal connected to a gate of the output terminal; the gate potential of the output transistor is set to be higher than a high-level potential of the clock signal during a period where the output transistor is ON and the clock signal is at a high level; and the control transistor includes a transistor that has a greater channel length than the output transistor (see Patent Literature 7).
Another disclosed shift register is a shift register including a plurality of cascade-connected shift register stages on a substrate, wherein the shift register stages each have a first transistor equipped with a capacitor electrode that faces at least one of source/drain electrodes in a thickness direction on the opposite side of a gate electrode, and the capacitor electrode and one of the source/drain electrodes facing the capacitor electrode are electrically connected to a control electrode of an output transistor of the shift register stage (see Patent Literature 8).
Disclosures related to one drop filling are mentioned below.
A disclosed liquid crystal display panel is a liquid crystal display panel including a TFT substrate, a CF substrate facing the TFT substrate, a sealing material sandwiched between the TFT substrate and the CF substrate and formed in a peripheral portion of the substrates, and a liquid crystal layer interposed between the TFT substrate and the CF substrate, wherein the CF substrate has a light shielding layer in the peripheral portion where the sealing material is provided and the light shielding layer has a gap in a region where the light shielding layer overlaps with a wiring of the TFT substrate (see Patent Literature 9).
Another disclosed liquid crystal display panel is a liquid crystal display panel including an active matrix substrate and a counter substrate facing each other, and a liquid crystal layer provided between the substrates to define a display region and a non-display region around the display region, wherein the non-display region includes a flame-like seal portion between the substrates, the seal portion has a narrow linear portion and a wide portion that is wider than the linear portion and is formed by a photocurable material; the active matrix substrate has a light-shielding display wiring patterned therein; and the counter substrate has a black matrix formed along the inner periphery of the seal portion and having a cutout at a position corresponding to the wide portion (see Patent Literature 10).